A programmable logic device (PLD) may be one example of an integrated circuit device. Programmable logic devices generally provide the user with the ability to configure the devices for look-up-table-type logic operations.
Early programmable logic devices were provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P TERM logic). As applications for which PLDs are used have increased in complexity, and as these devices have become larger, it has become more common to design PLDs to also include configurable specialized processing blocks, such as digital signal processing (DSP) blocks, in addition to blocks of generic programmable logic resources. It has also become more common to add dedicated circuits on the programmable devices for various commonly-used functions. Such dedicated circuits could include phase-locked loops or delay-locked loops for clock generation, as well as various circuits for various mathematical operations such as addition or multiplication.
Such programmable logic devices were configured using programming software that was provided to allow a user to lay out logic as desired and then translate that logic into a configuration for the programmable device. Such software also now commonly includes pre-defined functions, commonly referred to as “cores,” for configuring certain commonly-used structures, and particularly for configuring circuits for mathematical operations incorporating the aforementioned dedicated circuits. For example, cores may be provided for various trigonometric or algebraic functions.
Although available programming software may allow programming a device using a hardware description language, some programming software may allow for programming using a high-level programming language (HLL). One HLL that may be adopted for configuring a programmable device is OpenCL (Open Computing Language), although use of other high-level languages, and particularly other high-level synthesis languages, including C, C++, Fortran, C#, F#, BlueSpec and Matlab, also is within the scope of this invention. In OpenCL, for example, computation is performed using a combination of a host and kernels, where the host is responsible for input/output (I/O) and setup tasks, and kernels perform computation on independent inputs.
In any HLL, such as OpenCL, the kernel compiler may convert a kernel into a hardware circuit that implement an application from an OpenCL description. The compiler may parse, analyze, optimize, and implement a kernel as a high-performance pipelined circuit, suitable for implantation on a programmable device, such as an FPGA. The HLL compiler may generate a hardware-oriented data structure, such as a data flow graph. This data structure may represent a basic block module of circuitry on the programmable logic device. This data structure may also represent the kernel at a low level, and may contain information about its area and maximum clock frequency. The data flow graph can then be optimized to improve area and performance of the system, prior to RTL generation which may produce a Verilog HDL description of each kernel. In this process the HLL complier may use, e.g., existing Verilog or VHDL to implement primitive arithmetic operator units, including multiplication, division, addition, and subtraction or more complex functions like sine, cosine, or tangent.
DSP blocks may be spread across a programmable integrated circuit device, and the OpenCL compiler may be limited with respect to where arithmetic operator units may be placed on the device. For example, this may occur if, using the HLL compiler, the arithmetic operator units may only be placed within DSP blocks, or if the units may only be placed in logic fabric surrounding the DSP blocks on the programmable integrated circuit device. As used herein, an arithmetic operator may be any arithmetic operator unit such as a multiplier or an adder. In particular, most HLL to HDL compilers use only one of two kinds of arithmetic operators on the programmable integrated circuit device, either a arithmetic operator entirely based in logic fabric of a PLD or a arithmetic operator entirely based in DSP blocks of the PLD. Low level synthesis tools may not make use of both kinds of arithmetic operators because each kind of arithmetic operator may have different routing delays making it more difficult to get correct behavior from the set of arithmetic operators once the design has been simulated with generic HDL code.